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Sno
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Projects List
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IEEE
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1
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High - Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations
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2015
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2
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A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of Dct
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2015
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3
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Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes
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2015
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4
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Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For Dsrc Applications
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2015
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5
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Obfuscating Dsp Circuits Via High-Level Transformations
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2015
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6
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Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding
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2015
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7
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An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm For Reconfigurable Fir Filter Synthesis
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2015
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8
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Flexible Dsp Accelerator Architecture Exploiting Carry-Save Arithmetic
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2015
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9
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Low-Latency High-Throughput Systolic Multipliers Over For Nist Recommended Pentanomials
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2015
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10
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A Synergetic Use Of Bloom Filters For Error Detection And Correction
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2015
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11
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Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block
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2015
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12
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Recursive Approach To The Design Of A Parallel Self-Timed Adder
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2015
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13
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Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
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2015
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14
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Efficient Sub Quadratic Space Complexity Architectures For Parallel Mpb Single- And Double-Multiplications For All Trinomials Using Toeplitz Matrix-Vector Product Decomposition
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2015
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15
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Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications
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2015
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16
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Fast Sign Detection Algorithm For The Rns Moduli Set {2n+1 - 1, 2n - 1, 2n}
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2015
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17
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Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks
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2015
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18
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Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures
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2015
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19
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Novel Shared Multiplier Scheduling Scheme For Area-Efficient FFT/IFFT Processors
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2015
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20
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VLSI Computational Architectures For The Arithmetic Cosine Transform
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2015
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21
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A Generalization Of Addition Chains And Fast Inversions In Binary Fields
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2015
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22
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Low-Power And Area-Efficient Shift Register Using Pulsed Latches
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2015
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23
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Communication Optimization Of Iterative Sparse Matrix - Vector Multiply On GPUs And FPGAs
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2015
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24
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A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems
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2015
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25
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Low-Power Programmable PRPG With Test Compression Capabilities
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2015
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26
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One Minimum Only Trellis Decoder For Non – Binary Low - Density Parity - Check Codes
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2015
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27
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A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic
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2015
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28
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Mixing Drivers In Clock-Tree For Power Supply Noise Reduction
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2015
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29
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A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter For Sub-mW Energy Harvesting Applications
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2015
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30
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Simplified Trellis Min–Max Decoder Architecture For Nonbinary Low-Density Parity-Check Codes
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2015
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31
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New Regular Radix-8 Scheme For Elliptic Curve Scalar Multiplication Without Pre-Computation
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2015
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32
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Fault Tolerant Parallel Filters Based On Error Correction Codes
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2015
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33
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Comments On "Low-Latency Digit-Serial Systolic Double Basis Multiplier Over GF (2m ) Using Subquadrat Ic Toeplitz Matrix- Vector Product Approach"
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2015
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34
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Skewed-Load Test Cubes Based On Functional Broadside Tests For A Low-Power Test Set
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2015
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35
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Low-Complexity Tree Architecture For Finding The First Two Minima
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2015
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36
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Efficient Coding Schemes For Fault-Tolerant Parallel Filters
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2015
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37
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Piecewise-Functional Broadside Tests Based On Reachable States
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2015
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38
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A Multicycle Test Set Based On A Two-Cycle Test Set With Constant Primary Input Vectors
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2015
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39
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Partially Parallel Encoder Architecture For Long Polar Codes
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2015
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40
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Novel Block-Formulation And Area-Delay - Efficient Reconfigurable Interpolation Filter Architecture Formulti - Standard SDR Applications
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2015
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41
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An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator
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2014
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42
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Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip
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2014
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43
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A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits
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2014
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44
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Fast Radix-10 Multiplication Using Redundant BCD Codes
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2014
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45
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A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values
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2014
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46
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Multifunction Residue Architectures for Cryptography
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2014
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47
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Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
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2014
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48
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32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler
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2014
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49
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Recursive Approach to the Design of a Parallel Self-Timed Adder
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2014
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50
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Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
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2014
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51
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Statistical Analysis of MUX-Based Physical Unclonable Functions
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2014
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52
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Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme
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2014
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53
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Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation
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2014
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54
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Efficient Integer DCT Architectures for HEVC
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2014
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55
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Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm
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2014
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56
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A Method to Extend Orthogonal Latin Square Codes
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2014
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57
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Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter
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2014
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58
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Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
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2014
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59
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On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays
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2014
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60
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Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata
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2014
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61
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Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding
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2014
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62
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Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
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2014
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63
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Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes
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2014
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64
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Area–Delay–Power Efficient Carry-Select Adder
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2014
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65
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Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences
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2014
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66
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Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement
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2014
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67
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Digitally Controlled Pulse Width Modulator for On-Chip Power Management
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2014
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68
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Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States
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2014
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69
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Area-Delay Efficient Binary Adders in QCA
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2014
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70
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Sharing Logic for Built-In Generation of Functional Broadside Tests
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2014
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71
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Novel High Speed Vedic Mathematics Multiplier using compressors
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2013
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72
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Design of High Performance 64 bit MAC Unit
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2013
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73
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An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier
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2013
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74
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Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check(EG-LDPC)codes
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2013
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75
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Techniques for Compensating Memory Errors in JPEG2000
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2013
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76
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MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
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2013
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77
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Achieving Reduced Area By Multi-Bit Flip Flop Design
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2013
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78
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Design of Digital-Serial FIR Filters: Algorithms, Architecture and a CAD Tool
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2013
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79
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VLSI implementation of Fast Addition using Quaternary Signed Digit Number System
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2013
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80
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A low power single phase clock distribution using VLSI technology
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2013
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